1. Field of the Invention
The invention relates to a semiconductor process, and in particular to a structure and method for manufacturing devices having inverse T-shaped well regions.
2. Description of the Invention
Currently, development of the semiconductor IC process is trending towards extremely high density, wherein well-known MOS devices are fabricated by use of a deep sub-micron technology. The integrated circuits (ICs) which are manufactured under the appropriate circumstances in a process can avoid poor performance and can efficiently operate under normal conditions in line with the shrinkage of device sizes. Taking the above-mentioned MOS devices as an example, the entire design should be re-adjusted due to the shrinkage of the geometry structure, wherein a well region process is one of necessary approaches for manufacturing the MOS device in accord with the trend of miniaturization. Since punchthrough is often encountered and more precisely aligned MOS devices are required after MOS devices have been shrunk in size, the MOS devices are being manufactured by use of a well region process so as to meet the requirements of device specifications.
FIGS. 1 through 3 and FIGS. 4 through 6 illustrate two methods for manufacturing two conventional well structures.
Referring to FIG. 1, first, a lightly-doped diffusion region 12 is formed on a substrate 10 by an ion implantation process to define a well region. Since the part except for the formed well region is covered with a protective layer (not shown), the part mentioned above can not be affected by the ion-implantation process.
Next, two field oxide layers 14 are formed on the substrate 10 by an oxidation process or a trench-insulating technology, as shown in FIG. 2. The isolating oxide layers may also be formed by a trench-filling process. Therefore, the well region and its internal device region can be defined. Then, as shown in FIG. 3, the well region 16 is re-implanted by using the field oxide layers 14 as a mask to form a new impurity concentration distribution providing threshold voltage re-adjustment and punchthrough voltage control.
Referring to FIG. 4, there is shown a substrate 20 on which field oxide layers 22 for defining a device region are formed. As shown in FIG. 5, the substrate 20 is implanted with high energy to form a strip-shaped well region 24. The parts under field oxide layers 22 have a shallow impurity distribution and lighter concentration. Finally, referring to FIG. 6, the impurity concentration of the well region 28 is increased by another ion-implantation process, thereby adequately adjusting and controlling the threshold voltage.
However, the well region formed by the two processes mentioned above cannot avoid various problems caused by the re-shrinkage of devices. For example, when a gate oxide becomes thinner and the distance between a source and drain is reduced, a leakage current may exist between the gate and the source or drain, or between the drain and another electrode, such that power consumption is increased and accuracy of a logic operation is affected, even though the device is not at an on-state. In addition, since the ratio of channel length to the overlapping regions among the source, drain and gate is decreased, parasitic capacitance is increased and operational speed is slow. Furthermore, hot electron effect is easily encountered affecting the reliability of the devices, when the voltage on a channel is increased as the channel becomes shorter. In addition, the shallow junction structure adopted for preventing the narrow channel effect increases parasitic resistance. These problems await resolution.
In the first conventional well region process, since the implantation time and drive-in time for forming the entire well region are too long and the field oxide layers are formed after a channel stop implantation process, the narrow channel effect is readily encountered. Thus, the first conventional well region process is not suitable for manufacturing deep sub-micron devices. As for the second conventional process, since only field oxides are used as a mask for implantation, the impurity distributions under the gate and source/drain are the same, thus being not able to prevent various problems caused by device shrinkage. Consequently, the problems resulting from the conventional processes, such as current leakage, parasitic capacitance, and parasitic resistance, and even latch-up effect, must be overcome by a new approach and structure.